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Friday, July 12 • 9:55am - 10:15am
Practical Erase Suspension for Modern Low-latency SSDs

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As NAND flash technology continues to scale, flash-based SSDs have become key components in data-center servers. One of the main design goals for data-center SSDs is low read tail latency, which is crucial for interactive online services as a single query can generate thousands of disk accesses. Towards this goal, many prior works have focused on minimizing the effect of garbage collection on read tail latency. Such advances have made the other, less explored source of long read tails, block erase operation, more important. Prior work on erase suspension addresses this problem by allowing a read operation to interrupt an ongoing erase operation, to minimize its effect on read latency. Unfortunately, the erase suspension technique attempts to suspend/resume an erase pulse at an arbitrary point, which incurs additional hardware cost for NAND peripherals and reduces the lifetime of the device. Furthermore, we demonstrate this technique suffers a write starvation problem, using a real, production-grade SSD. To overcome these limitations, we propose alternative practical erase suspension mechanisms, leveraging the iterative erase mechanism used in modern SSDs, to suspend/resume erase operation at well-aligned safe points. The resulting design achieves a sub-200μs 99.999th percentile read tail latency for 4KB random I/O workload at queue depth 16 (70% reads and 30% writes). Furthermore, it reduces the read tail latency by about 5 over the baseline for the two data-center workloads that we evaluated with.


Shine Kim

Seoul National University and Samsung Electronics

Jonghyun Bae

Seoul National University

Hakbeom Jang

Sungkyunkwan University

Wenjing Jin

Seoul National University

Jeonghun Gong

Seoul National University

Seungyeon Lee

Samsung Electronics

Tae Jun Ham

Seoul National University

Jae W. Lee

Seoul National University

Friday July 12, 2019 9:55am - 10:15am PDT
USENIX ATC Track I: Grand Ballroom I–VI