Back To Schedule
Friday, July 12 • 11:25am - 11:45am
Pisces: A Scalable and Efficient Persistent Transactional Memory

Sign up or log in to save this to your schedule, view media, leave feedback and see who's attending!

Persistent transactional memory (PTM) programming model has recently been exploited to provide crash-consistent transactional interfaces to ease programming atop NVM. However, existing PTM designs either incur high reader-side overhead due to blocking or long delay in the writer side (efficiency), or place excessive constraints on persistent ordering (scalability). This paper presents Pisces, a read-friendly PTM that exploits snapshot isolation (SI) on NVM. The key design of Pisces is based on two observations: the redo logs of transactions can be reused as newer versions for the data, and an intuitive MVCC-based design has read deficiency. Based on the observations, we propose a dual-version concurrency control (DVCC) protocol that maintains up to two versions in NVM-backed storage hierarchy. Together with a three-stage commit protocol, Pisces ensures SI and allows more transactions to commit and persist simultaneously. Most importantly, it promises a desired feature: hiding NVM persistence overhead from reads and allowing nearly non-blocking reads. Experimental evaluation on an Intel 40-thread (20-core) machine with real NVM equipped shows that Pisces outperforms the state-of-the-art design (i.e., DUDETM) by up to 6.3× for micro-benchmarks and 4.6× for TPC-C new order transaction, and also scales much better. The persistency cost is from 19% to 50% for 40 threads.


Jinyu Gu

Shanghai Jiao Tong University

Qianqian Yu

Shanghai Jiao Tong University

Xiayang Wang

Shanghai Jiao Tong University

Zhaoguo Wang

Shanghai Jiao Tong University

Binyu Zang

Shanghai Jiao Tong University

Haibing Guan

Shanghai Jiao Tong University

Haibo Chen

Shanghai Jiao Tong University / Huawei Technologies Co., Ltd.

Friday July 12, 2019 11:25am - 11:45am PDT
USENIX ATC Track I: Grand Ballroom I–VI